| 欧盟限制某些有害物质的使用 | Compliant |
| ECCN (US) | 3A991.d |
| Part Status | Active |
| HTS | 8542.39.00.01 |
| Family Name | Stratix® V GX |
| Process Technology | 28nm |
| User I/Os | 696 |
| Number of Registers | 634000 |
| Operating Supply Voltage (V) | 0.85 |
| Shift Registers | Utilize Memory |
| Logic Elements | 420000 |
| Number of Multipliers | 512 (18x18) |
| Program Memory Type | SRAM |
| Embedded Memory (Kbit) | 37888 |
| Total Number of Block RAM | 1900 |
| EMACs | 2 |
| IP Core | Sub-frame Latency JPEG 2000 Encoder (BA130)|RLDRAM II Controller Core|SPAUI MAC|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB)|RapidIO to AXI Bridge Controller (RAB)|Viterbi Compiler, Low-Speed/Hybrid Serial Decoder |
| Provider Name | Altera/Barco Silex/Mobiveil, Inc/Commsonic |
| Device Logic Units | 420000 |
| Device Number of DLLs/PLLs | 24 |
| Transceiver Channels | 36 |
| Transceiver Speed (Gbps) | 14.1 |
| Dedicated DSP | 256 |
| PCIe | 2 |
| Programmability | Yes |
| Reprogrammability Support | Yes |
| Copy Protection | Yes |
| In-System Programmability | Yes |
| Speed Grade | 3 |
| Differential I/O Standards | HCSL|LVDS|LVPECL |
| Single-Ended I/O Standards | LVTTL|LVCMOS |
| External Memory Interface | RLDRAM II|RLDRAM III|DDR3 SDRAM|QDRII+SRAM|DDR2 SDRAM |
| Minimum Operating Supply Voltage (V) | 0.82 |
| Maximum Operating Supply Voltage (V) | 0.88 |
| I/O Voltage (V) | 1.25|1.5|1.35|3|2.5|1.8|1.2 |
| Minimum Operating Temperature (°C) | 0 |
| Maximum Operating Temperature (°C) | 85 |
| Supplier Temperature Grade | Commercial |
| Tradename | Stratix |
| Standard Package Name | BGA |
| Pin Count | 1517 |
| Supplier Package | FC-FBGA |
| Mounting | Surface Mount |
| Package Height | 2.7 |
| Package Length | 40 |
| Package Width | 40 |
| PCB changed | 1517 |
| Lead Shape | Ball |
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