| 欧盟限制某些有害物质的使用 | Compliant with Exemption |
| ECCN (US) | 3A001.a.7.a |
| Part Status | LTB |
| HTS | 8542.39.00.01 |
| Family Name | Stratix® II |
| User I/Os | 534 |
| Process Technology | 90nm |
| Number of I/O Banks | 8 |
| Operating Supply Voltage (V) | 1.2 |
| Shift Registers | Utilize Memory |
| Logic Elements | 90960 |
| Number of Multipliers | 192 (18x18) |
| Program Memory Type | SRAM |
| Embedded Memory (Kbit) | 4414.5 |
| Total Number of Block RAM | 4+408+488 |
| IP Core | PowerPC/SH/1960 System Controller|Viterbi Compiler, High-Speed Parallel Decoder|32/64-bit PCI-X bus Master/Target interface Core, 66/100/133Mhz|RapidIO to AXI Bridge Controller (RAB) |
| Provider Name | Altera/CAST, Inc/Barco Silex/Mobiveil, Inc/Eureka Technology Inc/PLDA |
| Device Logic Units | 90960 |
| Number of Global Clocks | 16 |
| Device Number of DLLs/PLLs | 12 |
| Dedicated DSP | 48 |
| Programmability | No |
| Reprogrammability Support | No |
| Copy Protection | No |
| Opr. Frequency (MHz) | 711.24 |
| In-System Programmability | Yes |
| Speed Grade | 4 |
| GMACs | 50.4 |
| Mega Multiply Accumulates per second | 50400 |
| Differential I/O Standards | LVDS|LVPECL |
| Single-Ended I/O Standards | LVTTL|SSTL|CMOS|HSTL |
| Maximum I/O Performance | 1Gbps |
| External Memory Interface | DDR2 SDRAM|QDRII+SRAM|DDR SDRAM|RLDRAM II |
| Minimum Operating Supply Voltage (V) | 1.15 |
| Maximum Operating Supply Voltage (V) | 1.25 |
| I/O Voltage (V) | 1.8|3.3|2.5|1.5 |
| Minimum Operating Temperature (°C) | -40 |
| Maximum Operating Temperature (°C) | 100 |
| Supplier Temperature Grade | Industrial |
| Tradename | Stratix |
| Standard Package Name | BGA |
| Pin Count | 780 |
| Supplier Package | FC-FBGA |
| Mounting | Surface Mount |
| Package Height | 3(Max) |
| Package Length | 29 |
| Package Width | 29 |
| PCB changed | 780 |
| Lead Shape | Ball |
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